I wanted to introduce process-local variables in RHDL, and I tried a lot of different ideas, but finally settled on this fairly simple syntax (which was also easy to implement): process(clk) { #process-local vars here c = 0 #c is now local to the process process_behavior { #process behavior here if clk.event and clk == '1' puts "rising edge of...

I wanted to introduce process-local variables in RHDL, and I tried a lot of different ideas, but finally settled on this fairly simple syntax (which was also easy to implement): process(clk) { #process-local vars here c = 0 #c is now local to the process process_behavior { #process behavior here if clk.event and clk == '1' puts "rising edge of...

Well, my post grad-school time of working on ‘projects’ (that’s what I told people when they asked me what I was going to do now, “I’m working on projects” I would reply.) has come to an end. I had two months to work on my own ‘projects’. I start a new job tomorrow. It’ll be nice to have...

Well, my post grad-school time of working on ‘projects’ (that’s what I told people when they asked me what I was going to do now, “I’m working on projects” I would reply.) has come to an end. I had two months to work on my own ‘projects’. I start a new job tomorrow. It’ll be nice to have...

I’ve been reading Steve Yegge’s blog lately. His latest post entitled: Moore’s Law is crap raises interesting questions about the future of software development and computing in general. He makes the case that programming languages need to be developed that can more adequately model parallelism. I agree with Steve: in order...

I’ve been reading Steve Yegge’s blog lately. His latest post entitled: Moore’s Law is crap raises interesting questions about the future of software development and computing in general. He makes the case that programming languages need to be developed that can more adequately model parallelism. I agree with Steve: in order...

In another move that makes RHDL look a lot like VHDL (and I'm not sure that's always a good thing ;-) I've introduced generics into RHDL. A generic is a piece of data passed into the construction (or instantiation) of a design element/circuit to customize it. Generics are distinct from Signals. A generic always has a default value. To...

In another move that makes RHDL look a lot like VHDL (and I'm not sure that's always a good thing ;-) I've introduced generics into RHDL. A generic is a piece of data passed into the construction (or instantiation) of a design element/circuit to customize it. Generics are distinct from Signals. A generic always has a default value. To...

I just finished making all the connections between the new RHDL 'frontend' and the RHDL backend simulation code and the following design with both behavioral elements (the AndGate and Invert), structural elements (NandGate) and hierarchy is working: require 'RHDL' include RHDL AndGate = model { inputs a, b outputs out define_behavior { out...

I just finished making all the connections between the new RHDL 'frontend' and the RHDL backend simulation code and the following design with both behavioral elements (the AndGate and Invert), structural elements (NandGate) and hierarchy is working: require 'RHDL' include RHDL AndGate = model { inputs a, b outputs out define_behavior { out...

As I said earlier, the more Ruby-ness that can be hidden from the user of RHDL (or any DSL, for that matter), the better. It's not that Ruby is bad, it's mostly an issue of aesthetics and consistency within the DSL as well as hiding details that the user doesn't care about. Consider the following RHDL circuit desciption: class AndGate < RHDL...

As I said earlier, the more Ruby-ness that can be hidden from the user of RHDL (or any DSL, for that matter), the better. It's not that Ruby is bad, it's mostly an issue of aesthetics and consistency within the DSL as well as hiding details that the user doesn't care about. Consider the following RHDL circuit desciption: class AndGate < RHDL...

I mentioned this briefly at the end of a previous post, but I thought I’d expand on it. Signal objects can be assigned values. Those values can be of various different types like Bit or even just plain old Integers. In RHDL we’d like the assignment semantics to look a lot like using the built-in = operator (at least at first...

I mentioned this briefly at the end of a previous post, but I thought I’d expand on it. Signal objects can be assigned values. Those values can be of various different types like Bit or even just plain old Integers. In RHDL we’d like the assignment semantics to look a lot like using the built-in = operator (at least at first...

Actually I finished jumping through all the hoops last month, Feburary 3, 2006 when I successfully defended my thesis entitled: Finding Minimum Energy Atomic Clusters using Social Insect-based Algorithms. (I’ve included a link to my thesis over in the sidebar on the right). All the programming for the thesis experiments was done in a...